The discrete circuits of an integrated circuit chip can be isolated from one another using shallow trenches formed in the semiconductor substrate. This technique is appropriately known as shallow trench isolation (STI). Many semiconductor chips have semiconductor devices of various sizes. In these semiconductor chips, the same sized semiconductor devices often are organized in distinct regions. For example, dynamic random access memory (DRAM) chips include array regions comprising relatively small memory cells and peripheral regions comprising relatively large devices, such as decoder circuitry and other peripheral circuitry. FIG. 1A provides a circuit diagram that illustrates this arrangement. As shown in FIG. 1A, a conventional DRAM includes a peripheral circuit region i and a memory cell array region 2.
The memory cell array region 2 includes memory cells formed at the intersections of word lines and bit lines. For convenience, only memory cell 3 formed at the intersection of a word line WL and bit lines BL and /BL is shown. The peripheral circuit region 1 includes various peripheral circuit elements for selecting memory cells, including memory cell 3, coupled to word line WL. For example, the peripheral circuit region 1 includes an p-channel field effect transistor (FET) 4 and a n-channel FET 5. The control gates of FETs 4 and 5 are each connected to selection circuitry 6. A first terminal of each of the FETs are connected in common to word line WL. A second terminal of the p-channel FET 4 receives a word line drive signal WDRV. A second terminal of the n-channel FET 5 is coupled to ground.
FIG. 1B illustrates a plan view of the DRAM of FIG. 1A with associated resist patterns 1' and 2' for forming peripheral circuit region 1 and memory cell array region 2, respectively. The resist pattern 2' corresponding to the memory cell array region 2 includes a plurality of relatively small individual resist areas, including individual resist area 3' corresponding to memory cell 3. Resist pattern 1', corresponding to the peripheral circuit region 1, has relatively large individual resist areas 4' and 5' corresponding to FETs 4 and 5, respectively. The large individual resist areas of resist pattern 1' are spaced further apart than the small individual resist areas of resist pattern 2'. Accordingly, relatively large peripheral circuit elements can be formed in peripheral circuit region 1 and relatively small memory cells can be formed in memory cell array region 2.
Several problems arise when different sized devices formed in a single semiconductor chip are isolated using trenches. For example, power dissipation may unduly limit circuit performance. Trenches with highly vertical profiles have sharp corners at their edges. The electrical field at these sharp corners differs, for example, from the electrical field near the center of the channel of a transistor, and, as a result, a lower threshold voltage occurs near the sharp corners. Consequently, a leakage current is produced because an operating current is not cut off effectively due to the lower threshold voltage. Relatively large devices that operate with large currents, such as the peripheral circuitry in a DRAM, produce a significant leakage current. The leakage current dissipates power in the chip resulting in inefficient operation. In order to suppress power dissipation, large devices may be isolated with trenches having a tapered profile to relax the corner angles and thus minimize the leakage current.
Smaller devices are less sensitive than larger devices to the detrimental effects of sharp corners. The characteristics of smaller devices, such as memory cells in an array, tend to depend more on the shape of the entire region rather than on a sharp corner in a local area. Moreover, tapered trenches can lead to misalignments in later processing steps that could cause the devices in denser arrays to malfunction. Therefore, smaller devices are preferably isolated with trenches having vertical profiles in order to ensure a very precise alignment without unduly sacrificing performance characteristics.
Vertical trenches and tapered trenches could be formed in the same semiconductor substrate by effecting two distinct etching steps, each requiring a separate lithography step to mask protected areas. This process is time consuming, inefficient, and expensive, among other disadvantages. Alternatively, vertical and tapered trenches could be formed by deposition film development during the etching step. However, such procedure is dependent upon numerous variables such as etching conditions, chamber seasoning, total loading of the substrate, micro-loading, among various other parameters, and therefore is extremely difficult to control.
Accordingly, there is a need to provide in a single semiconductor chip both vertical trenches to isolate small devices and tapered trenches to isolate large devices. Further, there is a need to achieve this result without requiring complicated and expensive processing.